Phase change RAM device and method for manufacturing the same

ABSTRACT

A phase change RAM device includes a semiconductor substrate having a phase change cell area and a voltage application area; a first oxide layer, a nitride layer and a second oxide layer sequentially formed on the semiconductor substrate; a first plug formed in the first oxide layer, the nitride layer and the second oxide layer of the phase change cell area; a second plug formed in the first oxide layer and the nitride layer of the voltage application area; a conductive line formed in the second oxide layer; a third oxide layer formed on the second oxide layer; a lower electrode shaped like a plug, the lower electrode being formed so as to directly make contact with the first plug; and a phase change layer and an upper electrode sequentially formed on the lower electrode in a pattern form.

FIELD OF THE INVENTION

The present invention relates to a phase change Random Access Memory(hereinafter, referred to as RAM) device and a method for manufacturinga phase change RAM device. More particularly, the present inventionrelates to a phase change RAM device that can prevent an increase incell size and a method for manufacturing such a phase change RAM device.

DESCRIPTION OF THE PRIOR ART

As is generally known, semiconductor memory devices may be classifiedinto volatile RAM devices, in which information is lost when power isturned-off, and non-volatile Read Only Memory (hereinafter, referred toas ROM) devices in which information is not lost when power isturned-off. Volatile RAM may include dynamic random access memory orDRAM and static random access memory or SRAM. Non-volatile RAM may alsoinclude flash memory such as an Electrically Erasable and ProgrammableROM (EEPROM).

While DRAM is an excellent memory device, it stores data using acapacitance effect and therefore requires a relatively high chargestorage capability. As is known, the ability of a capacitor to storeelectrical charge is directly related to the spacing between thecapacitor's electrodes, the material between the electrodes and the areaof the electrodes. For a given spacing and dielectric material, it isnecessary to increase electrode surface area in order to increasecapacitance. Therefore, it is difficult to highly integrate the DRAM.

Flash memory avoids some of the problems of DRAM but it requires anoperation voltage higher than a power supply voltage in relation to itsstructure having two stacked gates. Since flash memory requires aseparate boost circuit in order to generate voltage necessary for writeand erase operations, it too is difficult to highly integrate the flashmemory.

Much research has been actively conducted in order to develop a newmemory device, which can be highly integrated while having thecharacteristics of the non-volatile RAM device, and has a simplestructure. Recently, a phase change non-volatile RAM device has beenproposed as a new memory device.

In a phase change RAM device, a phase change layer interposed between alower electrode and an upper electrode changes from a crystalline stateto an amorphous state through electric current flow between theelectrodes. Herein, the phase change RAM device determines informationstored in a cell by means of resistance difference caused according tocrystalline and amorphousness.

In other words, the phase change RAM device uses a chalcogenide layer asa phase change layer. Such a chalcogenide layer corresponds to achemical compound layer made from Germanium (Ge), Stibium (Sb) andtellurium (Te), and experiences phase change between an amorphous stateand a crystalline state by applied electric current, i.e. Joule Heat.Herein, since a phase change layer with an amorphous state has specificresistance higher than that of a phase change layer with a crystallinestate, the phase change RAM device detects electric current flowingthrough the phase change layer in write and read modes, and determinesif information stored in a phase change memory cell represents logic “1”or “0”.

FIG. 1 is a sectional view illustrating a conventional proposed phasechange RAM device.

As illustrated in FIG. 1, gates 3 are formed on the active area of asemiconductor substrate 1 isolated by an isolation layer 2, andsource/drain areas 4 and 5 are formed under a substrate surface on bothsides of the gates 3.

A first oxide layer 6 is formed on the entire surface of the substrate 1in order to cover the gates 3, and a first tungsten plug 7 and a secondtungsten plug 8 are formed in the first oxide layer 6 on the drain area5 with which a phase change cell is to make contact and the source area4 to which voltage is to be applied.

A second oxide layer 9 is formed on the first oxide layer 6 includingthe first tungsten plug 7 and the second tungsten plug 8. Further, metalpads 10 shaped like dots and a conductive line 11 shaped like a bar areformed in the second oxide layer 9. In more detail, the metal pads 1.0are formed on predetermined areas on which the phase change cell is tobe formed according to a damascene process so that the metal pads 10 canmake contact with the first tungsten plug 7, and the conductive line 11is formed on a predetermined area to which voltage is to be applied sothat the conductive line 11 can make contact with the second tungstenplug 8.

A third oxide layer 12 is formed on the second oxide layer 9 includingthe metal pads 10 and the conductive line 11, and lower electrodes 13shaped like plugs are formed in the third oxide layer 12 of the areas onwhich the phase change cell is to be formed so that the lower electrodes13 can make contact with the metal pads 10.

Phase change layers 14 and upper electrodes 15 are laminated on thethird oxide layer 12 in a pattern form so that the phase change layers14 and the upper electrodes 15 can make contact with the lowerelectrodes 13. In this way, the phase change cell is formed, which iscomprised of the lower electrode 13, the phase change layer 14 laminatedon the lower electrode 13, and the upper electrode 15 laminated on thephase change layer 14.

Further, a fourth oxide layer 16 is formed on the third oxide layer 12in order to cover the phase change cell, and metal wires 17 for makingcontact with the upper electrodes 15 are formed on the fourth oxidelayer 16.

However, in the phase change RAM device, the metal pads and theconductive line must be simultaneously formed in the second oxide layeron the upper part of the drain area on which the phase change cell isformed and the upper part of the source area to which voltage isapplied. Since the metal pads and the conductive line are simultaneouslyformed in the same layer, it is necessary to ensure intervals betweenthe metal pads and the conductive line. Therefore, the cell sizeinevitably increases.

SUMMARY OF THE INVENTION

In light of the foregoing problems with the prior art, an object of thepresent invention to provide a phase change RAM device capable ofpreventing an increase in cell size and a method for manufacturing thephase change RAM device.

In order to achieve the above objects, according to one aspect of thepresent invention, there is provided a phase change Random Access Memory(RAM) device including: a semiconductor substrate having a phase changecell area and a voltage application area; a first oxide layer, a nitridelayer and a second oxide layer sequentially formed on the semiconductorsubstrate; a first plug formed in the first oxide layer, the nitridelayer and the second oxide layer of the phase change cell area; a secondplug formed in the first oxide layer and the nitride layer of thevoltage application area; a conductive line formed in the second oxidelayer on the second plug of the voltage application area; a third oxidelayer formed on the second oxide layer including the first plug and theconductive line; a lower electrode shaped like a plug, the lowerelectrode being formed so as to directly make contact with the firstplug in the third oxide layer of the phase change cell area; and a phasechange layer and an upper electrode sequentially formed on the lowerelectrode in a pattern form.

In the phase change RAM device, the phase change cell area correspondsto a drain area of a transistor, and the voltage application areacorresponds to a source area of the transistor.

In the phase change RAM device, the first plug, the second plug and theconductive line are made from tungsten.

In the phase change RAM device, the lower electrode is made from one ofTiN, TiW, Al, Cu and Wsi.

In the phase change RAM device, the phase change layer is made from oneof Ge—Sb—Te, Ge—Bi—Te, Sb—Te dope with at least one of Ag, In and Bi,and Bi—Te dope with at least one of Ag, In and Sn.

In the phase change RAM device, the upper electrode is made from one ofAl, Ti, Ta, TaSiN, TaN, Ru, TiN, TiW and TiAlN.

BRIEF DESCRIPTION OF THE DRAWINGS

The above and other objects, features and advantages of the presentinvention will be more apparent from the following detailed descriptiontaken in conjunction with the accompanying drawings, in which:

FIG. 1 is a sectional view illustrating a conventional phase change RAMdevice; and

FIGS. 2A to 2G are sectional views according to steps in a method formanufacturing a phase change RAM device based on the present invention.

DETAILED DESCRIPTION

Hereinafter, a preferred embodiment of the present invention will bedescribed with reference to the accompanying drawings.

FIGS. 2A to 2G are sectional views according to steps in a method formanufacturing a phase change RAM device based on the present invention.

Referring to FIG. 2A, an isolation layer 22 is formed in a semiconductorsubstrate 21 according to a shallow trench isolation (STI) process so asto isolate an active area. Then, gates 23 are formed on the active area,which are isolated by the isolation layer 22, according to a well-knownprocess, and a source area 24 and a drain area 25 are formed under asubstrate surface on both sides of the gates 3 through highconcentration ion implantation of impurity so as to create a transistor.

Next, a first oxide layer 26 is formed on the entire surface of thesubstrate 1 as an insulating interlayer in order to cover thetransistor, and the surface of the first oxide layer 26 is planarized byan etchback process or a Chemical Mechanical Polishing (hereinafter,referred to as CMP) process. Then, a nitride layer 27 is deposited onthe first oxide layer 26 with the planarized surface as an etch stoppinglayer, and a second oxide layer 28 is formed on the nitride layer 27.

Referring to FIG. 2B, the second oxide layer 28 is partially etched byusing the nitride layer 27 as an etch stopping layer. In this way, atrench 29 shaped like a bar for isolating an area, on which a conductiveline is to be formed, is formed above the source area 24 to whichvoltage is to be applied.

In the present invention, only the trench 29 shaped like a bar is formedwhile holes shaped like dots for forming metal pads are not formed abovethe drain area 25 in contact with a phase change cell, as compared withthe prior art. Therefore, it is not necessary to ensure intervalsbetween the metal pad and the conductive line. Accordingly, the presentinvention can prevent an increase in cell size, which may be caused byensuring the intervals between the metal pad and the conductive line.

Referring to FIG. 2C, in a state in which a mask pattern for exposingthe source area 24 and the drain area 25 has been formed on the secondoxide layer 28, the nitride layer 27 is etched by means of the maskpattern. Then, the second oxide layer 28 and the first oxide layer 26are etched, so that first contact holes 30 for exposing the drain area25 in a phase change cell area are formed, and a second contact hole 31for exposing the source area 24 in a voltage application area is formed.

Referring to FIG. 2D, a plug conductive layer, e.g. a tungsten layer, isdeposited on the second oxide layer 28 so as to completely fill in thetrench 29 including the first contact holes 30 and the second contacthole 31. Then, the plug conductive layer is subjected to an etchbackprocess or a CMP process so that first tungsten plugs 32 respectivelymaking contact with the drain area 25 are formed in the first contactholes 30, and a second tungsten plug 33 is formed in the second contacthole 31. Simultaneously, a conductive line 34 is formed in the trench29.

Herein, according to the present invention, the metal pad is not formedabove the drain area 25, so that it is possible to prevent an increasein cell size, which may be caused by ensuring the intervals between themetal pad and the conductive line. In addition, the conductive line 34and the tungsten plugs 32 and 33 are simultaneously formed, so that aprocess can be simplified, as compared with the prior art in which thetungsten plugs and the conductive line are respectively formed.

Referring to FIG. 2E, a third oxide layer 35 is formed on the secondoxide layer 28 including the first tungsten plug 32 and the conductiveline 34. Then, the third oxide layer 35 is etched so as to form a thirdcontact hole 36 for a lower electrode, which has a fine size and exposesthe first tungsten plugs 32 of an area in which a phase change cell isto be formed.

Since the third oxide layer 35 is formed on a generally planarizedunderlayer, i.e. the second oxide layer 28 including the first tungstenplug 32 and the conductive line 34, the third oxide layer 35 has acomparatively uniform thickness. Accordingly, it is possible to stablyperform an E-beam process when forming the third contact hole 36.

Referring to FIG. 2F, a lower electrode material layer is deposited onthe third oxide layer 35 so as to fill in the third contact hole 36,i.e. one of TiN, TiW, Al, Cu and Wsi is deposited on the third oxidelayer 35. Then, the lower electrode material layer is subjected to anetchback process, so that a lower electrode 37 is formed without aninterposition of a metal pad within the third contact hole 36. The lowerelectrode 37 has a shape of a plug and directly makes contact with thefirst tungsten plug 32.

Referring to FIG. 2G, the third oxide layer 35 including the lowerelectrode 37 is subjected to a Chemical Vapor Deposition (CVP) processor an Atomic Layer Deposition (ALP) process, so that a phase changematerial layer is deposited. The phase change material layer usesGe—Sb—Te or Ge—Bi—Te. Otherwise, the phase change material layer usesSb—Te dope with at least one of Ag, In and Bi, or Bi—Te dope with atleast one of Ag, In and Sn. Then, an upper electrode material layer,which contains Al, Ti, Ta, TaSiN, TaN, Ru, TiW, TiN, TiAlN, etc., isdeposited on the phase change material layer.

Then, the upper electrode material layer and the phase change materiallayer under the upper electrode material layer are etched so as to forman upper electrode 39 and a phase change layer 38. In this way, a phasechange cell is formed, which contains the lower electrode 37 shaped likea plug, the phase change layer 38 laminated on the lower electrode 37 ina pattern form, and the upper electrode 39 laminated on the phase changelayer 38 in a pattern form.

Then, a series of well-known subsequent processes including a metalwiring process are sequentially accomplished, so that the phase changeRAM device according to the present invention is completelymanufactured.

According to the present invention as described above, a lower electrodeshaped like plugs directly makes contact with a tungsten plug in contactwith a drain area, so that it is possible to prevent a metal pad frombeing formed. Therefore, it is not necessary to ensure intervals betweenthe metal pad and a conductive line on a source area to which voltage isapplied. Accordingly, it is possible to effectively prevent an increasein cell size, which may be caused by ensuring the intervals between themetal pad and the conductive line.

Further, according to the present invention as described above, since athird oxide layer in which a lower electrode shaped like a plug isformed has a uniform thickness, it is possible to easily perform anE-beam process when forming a contact hole for a lower electrode.Specifically, the lower electrode shaped like a plug can have a uniformsize throughout an entire area of a substrate through processstabilization, so that a contact area between the lower electrode and aphase change layer can have a uniform size throughout the entire area ofthe substrate. Accordingly, it is possible to lower the range of writecurrent necessary for phase change of the phase change layer.

The preferred embodiment of the present invention has been described forillustrative purposes, and those skilled in the art will appreciate thatvarious modifications, additions and substitutions are possible, withoutdeparting from the scope and spirit of the invention as disclosed in theaccompanying claims.

1. A phase change Random Access Memory (RAM) device comprising: asemiconductor substrate having a phase change cell area and a voltageapplication area; a first oxide layer, a nitride layer and a secondoxide layer sequentially formed on the semiconductor substrate; a firstplug formed in the first oxide layer, the nitride layer and the secondoxide layer of the phase change cell area; a second plug formed in thefirst oxide layer and the nitride layer of the voltage application area;a conductive line formed in the second oxide layer on the second plug ofthe voltage application area; a third oxide layer formed on the secondoxide layer including the first plug and the conductive line; a lowerelectrode shaped like a plug, the lower electrode being formed so as todirectly make contact with the first plug in the third oxide layer ofthe phase change cell area; and a phase change layer and an upperelectrode sequentially formed on the lower electrode in a pattern form.2. The phase change RAM device as claimed in claim 1, wherein the phasechange cell area corresponds to a drain area of a transistor, and thevoltage application area corresponds to a source area of the transistor.3. The phase change RAM device as claimed in claim 1, wherein the firstplug, the second plug and the conductive line are made from tungsten. 4.The phase change RAM device as claimed in claim 1, wherein the lowerelectrode is made from one of TiN, TiW, Al, Cu and Wsi.
 5. The phasechange RAM device as claimed in claim 1, wherein the phase change layeris made from one of Ge—Sb—Te, Ge—Bi—Te, Sb—Te dope with at least one ofAg, In and Bi, and Bi—Te dope with at least one of Ag, In and Sn.
 6. Thephase change RAM device as claimed in claim 1, wherein the upperelectrode is made from one of Al, Ti, Ta, TaSiN, TaN, Ru, TiN, TiW andTiAlN.
 7. A method for manufacturing a phase change Random Access Memory(RAM) device, the method comprising the steps of: providing asemiconductor substrate, the semiconductor substrate having an isolationlayer for isolating an active area, a gate formed on the active area,and source and drain areas formed under a substrate surface on bothsides of the gate; sequentially forming a first oxide layer, a nitridelayer and a second oxide layer on an entire surface of the semiconductorsubstrate; etching the second oxide layer using the nitride layer as anetch stopping layer, thereby forming a trench shaped like a bar on thesecond oxide layer above the source area; etching the first oxide layer,the nitride layer and the second oxide layer, thereby forming a firstcontact hole for exposing the drain area and a second contact hole forexposing the source area in a lower surface of the trench; filling in aconductive layer within the first contact hole, the second contact hole,and the trench, thereby forming a first plug making contact with thedrain area in the first contact hole, forming a second plug makingcontact with the source area in the second contact hole, and forming aconductive line in the trench; forming a third oxide layer on the secondoxide layer including the first plug and the conductive line; forming alower electrode shaped like a plug, the lower electrode directly makingcontact with the first plug in the third oxide layer above the drainarea; and sequentially forming a phase change layer and an upperelectrode on the lower electrode and the third oxide layer in a patternform, the third oxide layer being adjacent to the lower electrode. 8.The method as claimed in claim 7, wherein the first plug, the secondplug and the conductive line are made from tungsten.
 9. The method asclaimed in claim 7, wherein the lower electrode is made from one of TiN,TiW, Al, Cu and Wsi.
 10. The method as claimed in claim 7, wherein thephase change layer is made from one of Ge—Sb—Te, Ge—Bi—Te, Sb—Te dopewith at least one of Ag, In and Bi, and Bi—Te dope with at least one ofAg, In and Sn.
 11. The method as claimed in claim 7, wherein the upperelectrode is made from one of Al, Ti, Ta, TaSiN, TaN, Ru, TiN, TiW andTiAlN.